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| author |   Thierry Reding <treding@nvidia.com> | 2020-03-19 13:27:37 +0100 |
|---|---|---|
| committer |   Linus Walleij <linus.walleij@linaro.org> | 2020-03-27 11:46:06 +0100 |
| commit | 368b62f2fd077d4c7db09461e8e24f07491a513d (patch) | |
| tree | f41a2b2b9bd20bbbf2eb9d8149b06a8b4d3169d0 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | pinctrl: tegra: Renumber the GG.0 and GG.1 pins (diff) | |
| download | linux-dev-368b62f2fd077d4c7db09461e8e24f07491a513d.tar.xz linux-dev-368b62f2fd077d4c7db09461e8e24f07491a513d.zip | |
pinctrl: tegra: Add SFIO/GPIO programming on Tegra194
Prior to Tegra186, the selection of SFIO vs. GPIO modes was done as part
of the GPIO controller's register programming. Starting with Tegra186, a
pin is configured as GPIO or SFIO with a bit in a configuration register
of the pin controller.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20200319122737.3063291-10-thierry.reding@gmail.com
Tested-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions