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| author |   Rodrigo Vivi <rodrigo.vivi@intel.com> | 2017-09-19 14:57:03 -0700 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2017-09-19 16:04:56 -0700 |
| commit | 3b92e263dd4a38fa168d12a55ea4c8193483b884 (patch) | |
| tree | 1c9fabfa5a9c6bb7a77e3d4a84ae4d4c06a5765c /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/i915: Shrink cnl_ddi_buf_trans (diff) | |
| download | linux-dev-3b92e263dd4a38fa168d12a55ea4c8193483b884.tar.xz linux-dev-3b92e263dd4a38fa168d12a55ea4c8193483b884.zip | |
drm/i915/cnp: Display Wa #1179: WaHardHangonHotPlug
"CNL PCH chance of hang when software accesses south display
registers after hotplug is enabled.
Workaround: Program 0xC2000 bits 11:8 = 0xF before enabling
south display hotplug detection."
"Workaround only needs to be applied to pre-production steppings
used in graphics capable SKUs, but it is easier to apply to
everything, and does not hurt."
v2: Moving from clock gating to right before enabling
SHOTPLUG_CTL as it should be.
v3: Align with SOUTH_CHICKEN1 (DK) and consequently use proper
spaces on bits definition since other bits around already use
new style. And now that checkpatch is not noise anymore I also
fixed the reg read mask to avoid going over 80 chars.
Suggested-by: Ben Widawsky <ben@bwidawsk.net>
Cc: Ben Widawsky <ben@bwidawsk.net>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170919215703.25947-1-rodrigo.vivi@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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