diff options
| author |   José Roberto de Souza <jose.souza@intel.com> | 2021-05-24 14:48:05 -0700 |
|---|---|---|
| committer | José Roberto de Souza <jose.souza@intel.com> | 2021-05-25 10:32:07 -0700 |
| commit | 3cdef2a9f27df8d3b4f356f812732e43597ca293 (patch) | |
| tree | fba9074affd3cfc134b5f5a25744f6f0fb217ebe /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/i915/display/adl_p: Allow DC3CO in pipe and port B (diff) | |
| download | linux-dev-3cdef2a9f27df8d3b4f356f812732e43597ca293.tar.xz linux-dev-3cdef2a9f27df8d3b4f356f812732e43597ca293.zip | |
drm/i915/display/adl_p: Disable PSR2
We are missing the implementation of some workarounds to enabled PSR2
in Alderlake P, so to avoid any CI report of issues around PSR2
disabling it until all PSR2 workarounds are implemented.
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210524214805.259692-5-jose.souza@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions