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| author |   Peter De Schrijver <pdeschrijver@nvidia.com> | 2013-04-03 17:40:40 +0300 |
|---|---|---|
| committer |   Stephen Warren <swarren@nvidia.com> | 2013-04-04 16:10:49 -0600 |
| commit | 3e72771e210348fbd7ff0ea1b9e14cd88380c05b (patch) | |
| tree | 5bb1543197683bdcaf8c8b4c5221147f717a7b6f /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: tegra: Add PLL post divider table (diff) | |
| download | linux-dev-3e72771e210348fbd7ff0ea1b9e14cd88380c05b.tar.xz linux-dev-3e72771e210348fbd7ff0ea1b9e14cd88380c05b.zip | |
clk: tegra: move from a lock bit idx to a lock mask
PLLC2 and PLLC3 on Tegra114 have separate phaselock and frequencylock bits.
So switch to a lock mask to be able to test both at the same time.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions