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author | 2019-08-02 08:47:28 -0700 | |
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committer | 2019-08-02 08:47:28 -0700 | |
commit | 42d21900b39ceebf7be1512d02d915280ba2bba5 (patch) | |
tree | 913f7a39effcf9381f916595048f722de478dc49 /tools/perf/scripts/python/export-to-postgresql.py | |
parent | Merge tag 'arm-swiotlb-5.3' of git://git.infradead.org/users/hch/dma-mapping (diff) | |
parent | clk: renesas: cpg-mssr: Fix reset control race condition (diff) | |
download | linux-dev-42d21900b39ceebf7be1512d02d915280ba2bba5.tar.xz linux-dev-42d21900b39ceebf7be1512d02d915280ba2bba5.zip |
Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd:
"A few fixes for code that came in during the merge window or that
started getting exercised differently this time around:
- Select regmap MMIO kconfig in spreadtrum driver to avoid compile
errors
- Complete kerneldoc on devm_clk_bulk_get_optional()
- Register an essential clk earlier on mediatek mt8183 SoCs so the
clocksource driver can use it
- Fix divisor math in the at91 driver
- Plug a race in Renesas reset control logic"
* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: renesas: cpg-mssr: Fix reset control race condition
clk: sprd: Select REGMAP_MMIO to avoid compile errors
clk: mediatek: mt8183: Register 13MHz clock earlier for clocksource
clk: Add missing documentation of devm_clk_bulk_get_optional() argument
clk: at91: generated: Truncate divisor to GENERATED_MAX_DIV + 1
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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