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| author |   Jesse Barnes <jbarnes@virtuousgeek.org> | 2013-03-28 09:55:41 -0700 |
|---|---|---|
| committer |   Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-04-02 20:54:31 +0200 |
| commit | 453c542059cfa1988cabcf84f715307cd9789163 (patch) | |
| tree | 5d6019f071131d1e4f8e7953e62918f4127c622f /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/i915/dp: fix up VLV DP handling v2 (diff) | |
| download | linux-dev-453c542059cfa1988cabcf84f715307cd9789163.tar.xz linux-dev-453c542059cfa1988cabcf84f715307cd9789163.zip | |
drm/i915: panel power sequencing for VLV eDP v2
PPS register offsets have changed in Valleyview.
v2: don't clobber port select bits on VLV when fixing up PPS timings
don't bother with G4x PPS regs (Jani)
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions