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| author |   Will Deacon <will.deacon@arm.com> | 2018-08-22 21:40:30 +0100 |
|---|---|---|
| committer |   Catalin Marinas <catalin.marinas@arm.com> | 2018-09-11 16:49:10 +0100 |
| commit | 45a284bc5ee3d629b6da1498c2273cb22361416e (patch) | |
| tree | bc6dd47bd4a105654b6fd8821e513cf22b7e698e /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | arm64: tlb: Use last-level invalidation in flush_tlb_kernel_range() (diff) | |
| download | linux-dev-45a284bc5ee3d629b6da1498c2273cb22361416e.tar.xz linux-dev-45a284bc5ee3d629b6da1498c2273cb22361416e.zip | |
arm64: tlb: Add DSB ISHST prior to TLBI in __flush_tlb_[kernel_]pgtable()
__flush_tlb_[kernel_]pgtable() rely on set_pXd() having a DSB after
writing the new table entry and therefore avoid the barrier prior to the
TLBI instruction.
In preparation for delaying our walk-cache invalidation on the unmap()
path, move the DSB into the TLB invalidation routines.
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions