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| author |   Ramalingam C <ramalingam.c@intel.com> | 2021-11-16 09:48:17 -0800 |
|---|---|---|
| committer |   Matt Roper <matthew.d.roper@intel.com> | 2021-12-02 21:38:38 -0800 |
| commit | 4b19f6b728c7ae0cc285d2012d5aa1ab99be9b39 (patch) | |
| tree | 485c9b6df34a97e4ee4193df660e791173b4539e /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/i915/dg2: Add Wa_16011777198 (diff) | |
| download | linux-dev-4b19f6b728c7ae0cc285d2012d5aa1ab99be9b39.tar.xz linux-dev-4b19f6b728c7ae0cc285d2012d5aa1ab99be9b39.zip | |
drm/i915/dg2: Add Wa_16013000631
Invalidate IC cache through pipe control command as part of the ctx
restore flow through indirect ctx pointer.
v2:
- Move pipe control from xcs indirect context to the rcs indirect
context. We'll eventually need this on the CCS engines too, but
support for those hasn't landed yet.
Cc: Chris Wilson <chris.p.wilson@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211116174818.2128062-5-matthew.d.roper@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions