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| author |   Badhri Jagan Sridharan <badhri@google.com> | 2020-08-31 19:59:16 -0700 |
|---|---|---|
| committer |   Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2020-09-16 13:03:50 +0200 |
| commit | 57ce64668f5d6f30bdf4344f3c94e79b7de8eb58 (patch) | |
| tree | 3f0324e34acacbaa26dd8a77afb2c61ba7044b07 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | usb: typec: tcpci: Add support when hidden tx registers are inaccessible (diff) | |
| download | linux-dev-57ce64668f5d6f30bdf4344f3c94e79b7de8eb58.tar.xz linux-dev-57ce64668f5d6f30bdf4344f3c94e79b7de8eb58.zip | |
usb: typec: tcpci: update ROLE_CONTROL for DRP
ROLE_CONTROL register would not have the actual CC terminations
unless the port does not set ROLE_CONTROL.DRP. For DRP ports,
CC_STATUS.cc1/cc2 indicates the final terminations applied
when TCPC enters potential_connect_as_source/_sink.
For DRP ports, infer port role from CC_STATUS and set corresponding
CC terminations before setting the orientation.
Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Badhri Jagan Sridharan <badhri@google.com>
Link: https://lore.kernel.org/r/20200901025927.3596190-4-badhri@google.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions