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| author |   Bjorn Helgaas <bhelgaas@google.com> | 2019-03-06 15:30:11 -0600 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2019-03-06 15:30:11 -0600 |
| commit | 5d130e3dd8b6995e93aeb7a740709a46e7acf5df (patch) | |
| tree | 5626eb1d39b398bd6e485f65915219e24291fe7c /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | Merge branch 'pci/dpc' (diff) | |
| parent | x86/PCI: Fixup RTIT_BAR of Intel Denverton Trace Hub (diff) | |
| download | linux-dev-5d130e3dd8b6995e93aeb7a740709a46e7acf5df.tar.xz linux-dev-5d130e3dd8b6995e93aeb7a740709a46e7acf5df.zip | |
Merge branch 'pci/enumeration'
- Probe bridge window attributes only once at enumeration-time to fix
device accesses during rescan (Bjorn Helgaas)
- Return BAR size (not "size -1 ") from pci_size() to simplify code (Du
Changbin)
- Use config header type (not class code) identify bridges more reliably
(Honghui Zhang)
- Work around Intel Denverton incorrect Trace Hub BAR size reporting
(Alexander Shishkin)
* pci/enumeration:
x86/PCI: Fixup RTIT_BAR of Intel Denverton Trace Hub
PCI: Rely on config space header type, not class code
PCI: Make pci_size() return real BAR size
PCI: Probe bridge window attributes once at enumeration-time
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions