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| author |   Khem Raj <raj.khem@gmail.com> | 2021-06-06 15:09:40 -0700 |
|---|---|---|
| committer |   Palmer Dabbelt <palmerdabbelt@google.com> | 2021-06-12 17:20:49 -0700 |
| commit | 5d2388dbf84adebeb6d9742164be8d32728e4269 (patch) | |
| tree | e3410ea87a1c0c08eccdb169bbbdefa7e63958c6 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | riscv: Fix BUILTIN_DTB for sifive and microchip soc (diff) | |
| download | linux-dev-5d2388dbf84adebeb6d9742164be8d32728e4269.tar.xz linux-dev-5d2388dbf84adebeb6d9742164be8d32728e4269.zip | |
riscv32: Use medany C model for modules
When CONFIG_CMODEL_MEDLOW is used it ends up generating riscv_hi20_rela
relocations in modules which are not resolved during runtime and
following errors would be seen
[ 4.802714] virtio_input: target 00000000c1539090 can not be addressed by the 32-bit offset from PC = 39148b7b
[ 4.854800] virtio_input: target 00000000c1539090 can not be addressed by the 32-bit offset from PC = 9774456d
Signed-off-by: Khem Raj <raj.khem@gmail.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions