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| author |   Qipan Li <Qipan.Li@csr.com> | 2014-01-03 10:59:22 +0800 |
|---|---|---|
| committer |   Linus Walleij <linus.walleij@linaro.org> | 2014-01-08 10:48:38 +0100 |
| commit | 6225633d7154f6ce005e389ef0a80ee2cc644608 (patch) | |
| tree | 52d5c6dc9b0bd5e8e40aa561e3009e4552a68b2e /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | pinctrl: sunxi: Add Allwinner A20 clock output pin functions (diff) | |
| download | linux-dev-6225633d7154f6ce005e389ef0a80ee2cc644608.tar.xz linux-dev-6225633d7154f6ce005e389ef0a80ee2cc644608.zip | |
pinctrl: sirf: add lost usp1_uart_nostreamctrl group for atlas6
commit af614b2301f0e304 adds lost USP-based UART pin groups for prima2,
but missed usp1_uart_nostreamctrl group for atlas6, this patch fixes it.
this makes USP(Universal Serial Ports) port1 can work as uart without
stream ctrl.
Signed-off-by: Qipan Li <Qipan.Li@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions