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| author |   Wolfram Sang <wsa+renesas@sang-engineering.com> | 2021-11-10 20:15:52 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2021-11-19 11:27:58 +0100 |
| commit | 63494b6f98f26f45e0e7929654dd67d6715cc495 (patch) | |
| tree | 41fe9e71c33dc6ae19c4af7f9a3162c96b28638d /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: renesas: rcar-gen3: Add SDnH clock (diff) | |
| download | linux-dev-63494b6f98f26f45e0e7929654dd67d6715cc495.tar.xz linux-dev-63494b6f98f26f45e0e7929654dd67d6715cc495.zip | |
clk: renesas: r8a779a0: Add SDnH clock to V3U
Currently a pass-through clock but we will make it a real divider clock
in the next patches.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20211110191610.5664-4-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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