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| author |   Kishon Vijay Abraham I <kishon@ti.com> | 2019-12-16 15:27:09 +0530 |
|---|---|---|
| committer | Kishon Vijay Abraham I <kishon@ti.com> | 2020-01-08 12:58:06 +0530 |
| commit | 6825cfc94825c3170feef946e926f1551a8a25c9 (patch) | |
| tree | 77244d588a7bb77021a0f675c32595662f923085 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | phy: cadence: Sierra: Change MAX_LANES of Sierra to 16 (diff) | |
| download | linux-dev-6825cfc94825c3170feef946e926f1551a8a25c9.tar.xz linux-dev-6825cfc94825c3170feef946e926f1551a8a25c9.zip | |
phy: cadence: Sierra: Set cmn_refclk_dig_div/cmn_refclk1_dig_div frequency to 25MHz
Set cmn_refclk_dig_div/cmn_refclk1_dig_div frequency to 25MHz
as specified in "Common Module Clock Configurations" of the Cadence
Sierra 16FFC Multi-Protocol PHY PMA Specification. It is set to 25MHz
since the only user of Cadence Sierra SERDES, TI J721E SoC provides
input clock frequency of 100MHz. For other frequencies,
cmn_refclk_dig_div/cmn_refclk1_dig_div should be configured
based on the "Common Module Clock Configurations".
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions