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| author |   Rodrigo Vivi <rodrigo.vivi@intel.com> | 2015-01-12 10:14:30 -0800 |
|---|---|---|
| committer |   Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-01-15 01:36:17 +0100 |
| commit | 6caf36a4f4610b05b32c27b7cc21119fccd54dfa (patch) | |
| tree | 9ef7df7b4a1d5d47d8569c490b3930732d5d8b22 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/i915: PSR VLV/CHV: Remove condition checks that only applies to Haswell. (diff) | |
| download | linux-dev-6caf36a4f4610b05b32c27b7cc21119fccd54dfa.tar.xz linux-dev-6caf36a4f4610b05b32c27b7cc21119fccd54dfa.zip | |
drm/i915: PSR HSW/BDW: Fix inverted logic at sink main_link_active bit.
We have only two possible states with so many names and combinations that
might be confusing.
1 - Main link active / enabled / stand by / on
2 - Main link disabled / off / full off
Let's start organizing it by fixing a inverted logic when setting the sink bit.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Durgadoss R <durgadoss.r@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions