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authorIcenowy Zheng <icenowy@aosc.io>2017-09-10 20:40:06 +0800
committerMaxime Ripard <maxime.ripard@free-electrons.com>2017-09-17 12:03:08 +0200
commit70641ccad7d19b8229bf1cac33f5b8e03fdc7c5a (patch)
tree0077ec3c16bb9a68b6a1c4837384e0b54ae6ffe1 /tools/perf/scripts/python/export-to-postgresql.py
parentclk: sunxi-ng: add CLK_SET_RATE_UNGATE to all H3 PLLs (diff)
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clk: sunxi-ng: add CLK_SET_RATE_PARENT flag to H3 GPU clock
The GPU clock on H3 has only one parent, PLL-GPU, and the PLL is only the parent of the GPU clock. The GPU clock can be tweaked by tweaking the PLL-GPU clock. Add CLK_SET_RATE_PARENT flag to allow tweaking the GPU clock via tweaking PLL-CPU. Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks") Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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