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author | 2011-09-19 17:34:45 +0200 | |
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committer | 2011-10-06 12:34:05 +0200 | |
commit | 73ba85937b2a07b6401ba0b7ca06a112762de9f7 (patch) | |
tree | f4905768cf9cc469b79e92a3c7cf9dec2c6079b1 /tools/perf/scripts/python/export-to-postgresql.py | |
parent | EDAC, MCE, AMD: Simplify NB MCE decoder interface (diff) | |
download | linux-dev-73ba85937b2a07b6401ba0b7ca06a112762de9f7.tar.xz linux-dev-73ba85937b2a07b6401ba0b7ca06a112762de9f7.zip |
amd64_edac: Add a fix for Erratum 505
When accessing the scrub rate control register (F3x58) on F15h, the DRAM
controller selector (F1x10C[DctCfgSel]) has to point to DCT0 so that the
scrub rate configuration can take effect. See Erratum 505 in the AMD
F15h revision guide for more details.
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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