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| author |   Shengjiu Wang <shengjiu.wang@nxp.com> | 2022-07-01 17:32:36 +0800 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2022-07-05 13:00:37 +0100 |
| commit | 7bad8125549cda14d9ccf97d7d76f7ef6ac9d206 (patch) | |
| tree | 611a16eb31aa6dc6a87465399dd92d05ba3f6750 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ASoC: tegra20_ac97: Fix missing error code in tegra20_ac97_platform_probe() (diff) | |
| download | linux-dev-7bad8125549cda14d9ccf97d7d76f7ef6ac9d206.tar.xz linux-dev-7bad8125549cda14d9ccf97d7d76f7ef6ac9d206.zip | |
ASoC: fsl_utils: Add function to handle PLL clock source
i.MX8MQ/MN/MM/MP platforms typically have 2 AUDIO PLLs being
configured to handle 8kHz and 11kHz series audio rates.
Add common function in fsl_utils to handle these two PLL
clock source, which are needed by CPU DAI drivers
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Link: https://lore.kernel.org/r/1656667961-1799-2-git-send-email-shengjiu.wang@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions