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author | 2016-09-15 23:14:01 +0800 | |
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committer | 2016-09-18 21:13:35 +0200 | |
commit | 7e81bda23ac3c79b6cf747c195810900b45a77fc (patch) | |
tree | 0de412eee606239efcb7bc4cf87087316a518851 /tools/perf/scripts/python/export-to-postgresql.py | |
parent | drm/sun4i: dotclock: Fix clock rate read back calcation (diff) | |
download | linux-dev-7e81bda23ac3c79b6cf747c195810900b45a77fc.tar.xz linux-dev-7e81bda23ac3c79b6cf747c195810900b45a77fc.zip |
drm/sun4i: dotclock: Allow divider = 127
The dot clock divider is 7 bits wide, and the divider range is 1 ~ 127,
or 6 ~ 127 if phase offsets are used. The 0 register value also
represents a divider of 1 or bypass.
Make the end condition of the for loop inclusive of 127 in the
round_rate callback.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions