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authorChen-Yu Tsai <wens@csie.org>2016-09-15 23:14:01 +0800
committerMaxime Ripard <maxime.ripard@free-electrons.com>2016-09-18 21:13:35 +0200
commit7e81bda23ac3c79b6cf747c195810900b45a77fc (patch)
tree0de412eee606239efcb7bc4cf87087316a518851 /tools/perf/scripts/python/export-to-postgresql.py
parentdrm/sun4i: dotclock: Fix clock rate read back calcation (diff)
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drm/sun4i: dotclock: Allow divider = 127
The dot clock divider is 7 bits wide, and the divider range is 1 ~ 127, or 6 ~ 127 if phase offsets are used. The 0 register value also represents a divider of 1 or bypass. Make the end condition of the for loop inclusive of 127 in the round_rate callback. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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