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author | 2019-07-12 18:09:19 -0700 | |
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committer | 2019-07-26 15:02:17 -0700 | |
commit | 98a5c2a3582a86d5acdcdeabbe0e6278e712201e (patch) | |
tree | 69a3b06d302a0a3eaf1f0befbe66bfff59108e1f /tools/perf/scripts/python/export-to-postgresql.py | |
parent | drm/i915/uc: Remove redundant RSA offset definition (diff) | |
download | linux-dev-98a5c2a3582a86d5acdcdeabbe0e6278e712201e.tar.xz linux-dev-98a5c2a3582a86d5acdcdeabbe0e6278e712201e.zip |
drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization
According to the spec when initializing the display in TGL we should not
set PORT_CL_DW12 for the Aux channel of the combo PHYs. We will re-use the
power well hooks from ICL so only set this register on gen < 12.
v2: Generalize check for gen 12 (suggested by José)
v3: Rebase after enum phy introduction
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190713010940.17711-2-lucas.demarchi@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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