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| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2021-06-10 15:46:29 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-06-10 15:46:29 +0200 |
| commit | 9c094430b9a6478b9a36b747d98331c03e08e623 (patch) | |
| tree | e12873e394cebfee143fb510c523eaa3e29e451b /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: renesas: Add CPG core wrapper for RZ/G2L SoC (diff) | |
| parent | dt-bindings: clock: Add r9a07g044 CPG Clock Definitions (diff) | |
| download | linux-dev-9c094430b9a6478b9a36b747d98331c03e08e623.tar.xz linux-dev-9c094430b9a6478b9a36b747d98331c03e08e623.zip | |
Merge tag 'renesas-r9a07g044-dt-binding-defs-tag' into renesas-clk-for-v5.14
Renesas RZ/G2L DT Binding Definitions
Clock definitions for the Renesas RZ/G2L (R9A07G044) SoC, shared by
driver and DT source files.
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions