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authorAharon Landau <aharonl@nvidia.com>2022-02-15 19:55:32 +0200
committerJason Gunthorpe <jgg@nvidia.com>2022-02-23 14:59:13 -0400
commit9ee2516c43823652da597633aed9646dac51c1f8 (patch)
treea0ae693e2d20aa05b6e84004bf51da5f3ffc8f7f /tools/perf/scripts/python/export-to-postgresql.py
parentRDMA/mlx5: Merge similar flows of allocating MR from the cache (diff)
downloadlinux-dev-9ee2516c43823652da597633aed9646dac51c1f8.tar.xz
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RDMA/mlx5: Store ndescs instead of the translation table size
Currently, ent->xlt stores the translation table size. This data should not be stored in the cache entry but be written directly to the mailbox. Store ndescs instead, and deduce the translation table size from it according to the access mode. Link: https://lore.kernel.org/r/e9dbfaa1f279793a6bd28ee5a31cb4f0f0d70f05.1644947594.git.leonro@nvidia.com Signed-off-by: Aharon Landau <aharonl@nvidia.com> Signed-off-by: Leon Romanovsky <leonro@nvidia.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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