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| author |   Jeffrey Hugo <quic_jhugo@quicinc.com> | 2022-05-11 09:23:19 -0600 |
|---|---|---|
| committer |   Wei Liu <wei.liu@kernel.org> | 2022-05-11 17:51:02 +0000 |
| commit | a2bad844a67b1c7740bda63e87453baf63c3a7f7 (patch) | |
| tree | c9e7f2de5f20aa27238d60c7829f06f40384e28b /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | PCI: hv: Reuse existing IRTE allocation in compose_msi_msg() (diff) | |
| download | linux-dev-a2bad844a67b1c7740bda63e87453baf63c3a7f7.tar.xz linux-dev-a2bad844a67b1c7740bda63e87453baf63c3a7f7.zip | |
PCI: hv: Fix interrupt mapping for multi-MSI
According to Dexuan, the hypervisor folks beleive that multi-msi
allocations are not correct. compose_msi_msg() will allocate multi-msi
one by one. However, multi-msi is a block of related MSIs, with alignment
requirements. In order for the hypervisor to allocate properly aligned
and consecutive entries in the IOMMU Interrupt Remapping Table, there
should be a single mapping request that requests all of the multi-msi
vectors in one shot.
Dexuan suggests detecting the multi-msi case and composing a single
request related to the first MSI. Then for the other MSIs in the same
block, use the cached information. This appears to be viable, so do it.
Suggested-by: Dexuan Cui <decui@microsoft.com>
Signed-off-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Reviewed-by: Dexuan Cui <decui@microsoft.com>
Tested-by: Michael Kelley <mikelley@microsoft.com>
Link: https://lore.kernel.org/r/1652282599-21643-1-git-send-email-quic_jhugo@quicinc.com
Signed-off-by: Wei Liu <wei.liu@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions