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authorLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>2013-10-17 23:54:07 +0200
committerMike Turquette <mturquette@linaro.org>2013-12-12 19:23:58 -0800
commitabe844aa5bb50444ac3e02aed89b431823d6ad56 (patch)
tree4ac49f2cbbb3f16e0714f39a8447874e108a9180 /tools/perf/scripts/python/export-to-postgresql.py
parentclk: shmobile: Add R-Car Gen2 clocks support (diff)
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clk: shmobile: Add DIV6 clock support
DIV6 clocks are divider gate clocks controlled through a single register. The divider is expressed on 6 bits, hence the name, and can take values from 1/1 to 1/64. Those clocks are found on Renesas ARM SoCs. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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