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| author |   Will Deacon <will.deacon@arm.com> | 2018-08-23 21:16:50 +0100 |
|---|---|---|
| committer |   Catalin Marinas <catalin.marinas@arm.com> | 2018-09-11 16:49:12 +0100 |
| commit | ace8cb754539077ed75f3f15b77b2b51b5b7a431 (patch) | |
| tree | bab41795267bc907a837e48799405ee489672604 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | arm64: tlb: Adjust stride and type of TLBI according to mmu_gather (diff) | |
| download | linux-dev-ace8cb754539077ed75f3f15b77b2b51b5b7a431.tar.xz linux-dev-ace8cb754539077ed75f3f15b77b2b51b5b7a431.zip | |
arm64: tlb: Avoid synchronous TLBIs when freeing page tables
By selecting HAVE_RCU_TABLE_INVALIDATE, we can rely on tlb_flush() being
called if we fail to batch table pages for freeing. This in turn allows
us to postpone walk-cache invalidation until tlb_finish_mmu(), which
avoids lots of unnecessary DSBs and means we can shoot down the ASID if
the range is large enough.
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions