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| author |   James Zhu <James.Zhu@amd.com> | 2021-05-18 10:58:22 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2021-05-20 17:02:52 -0400 |
| commit | b95f045ea35673572ef46d6483ad8bd6d353d63c (patch) | |
| tree | a7e430e2314461503ef9421d22095287aa9e07ce /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/amdkfd: correct sienna_cichlid SDMA RLC register offset error (diff) | |
| download | linux-dev-b95f045ea35673572ef46d6483ad8bd6d353d63c.tar.xz linux-dev-b95f045ea35673572ef46d6483ad8bd6d353d63c.zip | |
drm/amdgpu/vcn1: add cancel_delayed_work_sync before power gate
Add cancel_delayed_work_sync before set power gating state
to avoid race condition issue when power gating.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions