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| author |   Xingyu Chen <xingyu.chen@amlogic.com> | 2017-11-16 17:01:15 +0800 |
|---|---|---|
| committer |   Kevin Hilman <khilman@baylibre.com> | 2017-12-06 17:03:47 -0800 |
| commit | b9b9db02018d5eddb06cf5e0fed9f70bd07b5900 (patch) | |
| tree | e4032e9fc6442a7ac6eaeb9c46e104a445c48941 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ARM: dts: meson8: add more L2 cache settings (diff) | |
| download | linux-dev-b9b9db02018d5eddb06cf5e0fed9f70bd07b5900.tar.xz linux-dev-b9b9db02018d5eddb06cf5e0fed9f70bd07b5900.zip | |
ARM: dts: meson: drop "sana" clock from SAR ADC
The SAR ADC modules doesn't require The "sana" clock.
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions