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| author |   Jani Nikula <jani.nikula@intel.com> | 2012-12-04 16:36:28 +0200 |
|---|---|---|
| committer |   Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-12-04 22:30:25 +0100 |
| commit | bfd7590d3eed3650e910a22a92dc23ea50e60a41 (patch) | |
| tree | 181e4a24af76a22264a9cf017657b190a9cf2cb1 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/i915: Don't allow ring tail to reach the same cacheline as head (diff) | |
| download | linux-dev-bfd7590d3eed3650e910a22a92dc23ea50e60a41.tar.xz linux-dev-bfd7590d3eed3650e910a22a92dc23ea50e60a41.zip | |
drm/i915: do not access BLC_PWM_CTL2 on pre-gen4 hardware
The BLC_PWM_CTL2 register does not exist before gen4. While at it, do a
slight drive by cleanup of the code.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions