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author | 2016-08-30 17:58:01 +0300 | |
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committer | 2016-08-31 07:37:40 -0700 | |
commit | c097338ebd3f7a0920dbe1a5d9bf276207f7b024 (patch) | |
tree | a1ce6866656760d583a79351d6be0c0e54aa6cab /tools/perf/scripts/python/export-to-postgresql.py | |
parent | ARM: dts: dra7: Fix clock data for gmac_gmii_ref_clk_div (diff) | |
download | linux-dev-c097338ebd3f7a0920dbe1a5d9bf276207f7b024.tar.xz linux-dev-c097338ebd3f7a0920dbe1a5d9bf276207f7b024.zip |
ARM: dts: dra7: cpsw: fix clocks tree
Current clocks tree definition for CPSW/CPTS doesn't
correspond TRM for dra7/am57 SoCs.
CPTS: has to be sourced from gmac_rft_clk_mux clock
CPSW: DPLL_GMAC -> CLKOUT_M2 -> GMAC_250M_CLK -> 1/2 ->
-> GMAC_MAIN_CLK (125 MHZ)
Hence, correct clock tree for GMAC_MAIN_CLK and use proper
clock for CPTS. This also require updating of CPTS clock
multiplier.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions