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author | 2018-08-20 21:40:13 +0800 | |
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committer | 2018-09-05 08:59:57 +0200 | |
commit | c2ff8383cc33c2d9c169e4daf1e37a434c3bb420 (patch) | |
tree | f4397980f281aa068cfc55d050854f3bbd087d17 /tools/perf/scripts/python/export-to-postgresql.py | |
parent | clk: sunxi-ng: a83t: Add max. rate constraint to video PLLs (diff) | |
download | linux-dev-c2ff8383cc33c2d9c169e4daf1e37a434c3bb420.tar.xz linux-dev-c2ff8383cc33c2d9c169e4daf1e37a434c3bb420.zip |
clk: sunxi-ng: sun50i: h6: Add 2x fixed post-divider to MMC module clocks
On the H6, the MMC module clocks are fixed in the new timing mode,
i.e. they do not have a bit to select the mode. These clocks have
a 2x divider somewhere between the clock and the MMC module.
To be consistent with other SoCs supporting the new timing mode,
we model the 2x divider as a fixed post-divider on the MMC module
clocks.
This patch adds the post-dividers to the MMC clocks, following the
approach on A64.
Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions