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authorHans de Goede <hdegoede@redhat.com>2018-02-25 11:46:48 +0100
committerMark Brown <broonie@kernel.org>2018-03-01 19:13:01 +0000
commitd082174c99e77beb06a51c90ac61934554e516e1 (patch)
treec0d3c249151b2d117d2510d7535733433547f253 /tools/perf/scripts/python/export-to-postgresql.py
parentASoC: rt5651: Add rt5651_apply_properties() helper function (diff)
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ASoC: rt5651: Remove is_sys_clk_from_pll()
is_sys_clk_from_pll() is used as a snd_soc_dapm_route.connected callback, checking RT5651_GBL_CLK to determine if the sys-clk is PLL1 and thus the PWR_PLL bit in reg PWR_ANLG2 must be set. RT5651_GBL_CLK is changed by rt5651_set_dai_sysclk(), which gets called by the pre_pmu / post_pmd functions of the "Platform Clock" dapm-supply. This creates an ordering issue, during a dapm transition first all connected() callbacks are called to build a list of supplies to enable and then the complete list is walked to enable the supplies. Since the connected() check happens before enabling any supplies, is_sys_clk_from_pll() ends up deciding if the PWR_PLL bit should be set based on the state the "Platform Clock" supply had *before* the transition. This sometimes results in PWR_PLL being off, even though *after* the transition PLL1 is configured as sys-clk. This commit removes is_sys_clk_from_pll() instead simply setting / clearing PWR_PLL in rt5651_set_dai_sysclk() based on the selected sys-clk, which fixes this and as a bonus results in a nice cleanup. Tested-by: Carlo Caione <carlo@endlessm.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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