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author | 2020-11-20 15:33:19 +0100 | |
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committer | 2020-12-11 21:13:08 +0530 | |
commit | e0ebdbdcb42a66f49b7587dc50cc6f528ec55cad (patch) | |
tree | 579c34397afd3f4551462f47fab13e66e0824186 /tools/perf/scripts/python/export-to-postgresql.py | |
parent | dmaengine: stm32-dma: clean channel configuration when channel is freed (diff) | |
download | linux-dev-e0ebdbdcb42a66f49b7587dc50cc6f528ec55cad.tar.xz linux-dev-e0ebdbdcb42a66f49b7587dc50cc6f528ec55cad.zip |
dmaengine: stm32-dma: take address into account when computing max width
DMA_SxPAR or DMA_SxM0AR/M1AR registers have to be aligned on PSIZE or MSIZE
respectively. This means that bus width needs to be forced to 1 byte when
computed width is not aligned with address.
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Link: https://lore.kernel.org/r/20201120143320.30367-4-amelie.delaunay@st.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions