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author | 2021-08-16 05:02:28 +0000 | |
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committer | 2021-08-16 13:28:14 +0100 | |
commit | ed14666c3f877c4c2a428a92bfeebfba3a4cfe2e (patch) | |
tree | f1ce5ac66a25a9783286e97cf6c95fb2c1f50e77 /tools/perf/scripts/python/export-to-postgresql.py | |
parent | spi: cadence-quadspi: Fix check condition for DTR ops (diff) | |
download | linux-dev-ed14666c3f877c4c2a428a92bfeebfba3a4cfe2e.tar.xz linux-dev-ed14666c3f877c4c2a428a92bfeebfba3a4cfe2e.zip |
spi: orion: Prevent incorrect chip select behaviour
When clearing the chip-select mask, the controller will switch to chip
selecting the native CS0 line. Because the control register chip-select
mask is not updated in a single write this will cause undesirable
chip-selection of CS0 even when requesting to select other native
chip-select lines. This is additionally problematic as the chip-select
may still be asserted. With the ARMADA 38x SoC the controller will
assert both the desired native chip-select and CS0.
To avoid any undesirable behaviour with the chip-select lines, update
the control register with a single write. This avoids selecting CS0 and
causes the (de-)assert to apply at the same time.
Signed-off-by: Nathan Rossi <nathan.rossi@digi.com>
Link: https://lore.kernel.org/r/20210816050228.3223661-1-nathan@nathanrossi.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions