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authorThierry Reding <treding@nvidia.com>2019-07-26 12:16:16 +0200
committerThierry Reding <treding@nvidia.com>2019-10-29 20:30:05 +0100
commiteef97c2a77febcccd3a9d70b9a6856ad43c7c069 (patch)
tree61ed060e1f75e79383ea92d95bd03a5e2a94af4e /tools/perf/scripts/python/export-to-postgresql.py
parentarm64: tegra: Add CPU and cache topology for Tegra194 (diff)
downloadlinux-dev-eef97c2a77febcccd3a9d70b9a6856ad43c7c069.tar.xz
linux-dev-eef97c2a77febcccd3a9d70b9a6856ad43c7c069.zip
arm64: tegra: Add unit-address for CBB on Tegra194
The control back-bone (CBB) starts at physical address 0, so give it a unit-address to comply with standard naming practices checked for by the device tree compiler. Signed-off-by: Thierry Reding <treding@nvidia.com>
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