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author | 2019-07-26 12:16:16 +0200 | |
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committer | 2019-10-29 20:30:05 +0100 | |
commit | eef97c2a77febcccd3a9d70b9a6856ad43c7c069 (patch) | |
tree | 61ed060e1f75e79383ea92d95bd03a5e2a94af4e /tools/perf/scripts/python/export-to-postgresql.py | |
parent | arm64: tegra: Add CPU and cache topology for Tegra194 (diff) | |
download | linux-dev-eef97c2a77febcccd3a9d70b9a6856ad43c7c069.tar.xz linux-dev-eef97c2a77febcccd3a9d70b9a6856ad43c7c069.zip |
arm64: tegra: Add unit-address for CBB on Tegra194
The control back-bone (CBB) starts at physical address 0, so give it a
unit-address to comply with standard naming practices checked for by the
device tree compiler.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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