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| author |   Biju Das <biju.das.jz@bp.renesas.com> | 2022-04-02 08:46:24 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2022-04-13 12:30:18 +0200 |
| commit | f201eb84450f98decb1834e73409bb2271441dd7 (patch) | |
| tree | 675474ea424415a2df8320754aa66ef832bc9641 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: renesas: r9a07g043: Add GPIO clock and reset entries (diff) | |
| download | linux-dev-f201eb84450f98decb1834e73409bb2271441dd7.tar.xz linux-dev-f201eb84450f98decb1834e73409bb2271441dd7.zip | |
clk: renesas: r9a07g043: Add ethernet clock sources
Ethernet reference clock can be sourced from PLL5_500 or PLL6. Add
support for ethernet source clock selection using SEL_PLL_6_2 mux.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220402074626.25624-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions