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| author |   Biju Das <biju.das.jz@bp.renesas.com> | 2022-04-02 09:13:24 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2022-04-13 13:56:09 +0200 |
| commit | 20e63d3948985672b9e8efa98ff3643d91378e84 (patch) | |
| tree | a9d8f212f6d768637703345531c34db6c9b1de02 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | arm64: dts: renesas: rzg2ul-smarc: Add scif0 and audio clk pins (diff) | |
| download | linux-dev-20e63d3948985672b9e8efa98ff3643d91378e84.tar.xz linux-dev-20e63d3948985672b9e8efa98ff3643d91378e84.zip | |
arm64: dts: renesas: r9a07g043: Add SDHI nodes
Add SDHI{0, 1} nodes to RZ/G2UL SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220402081328.26292-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions