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| author |   Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2018-08-31 18:37:47 +0200 |
|---|---|---|
| committer |   Thierry Reding <treding@nvidia.com> | 2018-09-26 16:45:41 +0200 |
| commit | 7890d7856a989a7f2a4c46ec84c4ecda6a760c11 (patch) | |
| tree | e4b0c770cfa9fc0b6c5140e010203ba2fc26c1c4 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | ARM: tegra: apalis_t30: reorder pcie properties (diff) | |
ARM: tegra: apalis_t30: annotate/clean-up pcie controller/port nodes
Annotate PCIe port nodes and clean-up PCIe controller/port status' with
respect to carrier board vs. module level device trees. As port 3
connects to the on-module Gigabit Ethernet MACPHY it is always enabled
together with the PCIe controller itself.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions