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| author |   Mauro Rossi <issor.oruam@gmail.com> | 2020-07-11 21:28:48 +0200 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2020-07-27 16:45:44 -0400 |
| commit | f233c09842bc91a8f7f5dfadc6de77f52273befc (patch) | |
| tree | 5f99abb6c1368af43fd6f9e4d1b23ac8884319b5 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | drm/amdgpu: add some required DCE6 registers (v7) (diff) | |
drm/amd/display: add asics info for SI parts
[Why]
Asic info for SI parts need to be preliminarly added
[How]
Asics info retrieved from si_id.h in https://github.com/GPUOpen-Tools/CodeXL
Tree path:
./CodeXL/Components/ShaderAnalyzer/AMDTBackEnd/Include/Common/asic_reg/si_id.h
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions