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| author |   Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> | 2018-09-05 19:59:48 +0300 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2018-09-11 11:58:02 +0200 |
| commit | 5986b503da614df3fccbf90edab3afa4c7550fa1 (patch) | |
| tree | 5b51a6c2d5a198ca7aa0712dd3adc17013e766f2 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | clk: renesas: r9a06g032: Fix UART34567 clock rate (diff) | |
| download | linux-dev-5986b503da614df3fccbf90edab3afa4c7550fa1.tar.xz linux-dev-5986b503da614df3fccbf90edab3afa4c7550fa1.zip | |
clk: renesas: r8a77970: Add CMT clocks
Add the R8A77970 CMT module clocks.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Chris Paterson <chris.paterson2@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions