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| author |   Sam McNally <sammc@chromium.org> | 2019-09-17 15:49:33 +1000 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2019-10-01 12:08:49 +0100 |
| commit | adebb11139029ddf1fba6f796c4a476f17eacddc (patch) | |
| tree | 9ba9107fe58e0783c569cb49b94a1806f259c841 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | ASoC: fsl_mqs: Add MQS component driver (diff) | |
ASoC: Intel: cht_bsw_rt5645: Add quirk for boards using pmc_plt_clk_0
As of commit 648e921888ad ("clk: x86: Stop marking clocks as
CLK_IS_CRITICAL"), the cht_bsw_rt5645 driver needs to enable the clock
it's using for the codec's mclk. It does this from commit 7735bce05a9c
("ASoC: Intel: boards: use devm_clk_get() unconditionally"), enabling
pmc_plt_clk_3. However, Strago family Chromebooks use pmc_plt_clk_0 for
the codec mclk, resulting in white noise with some digital microphones.
Add a DMI-based quirk for Strago family Chromebooks to use pmc_plt_clk_0
instead - mirroring the changes made to cht_bsw_max98090_ti in
commit a182ecd3809c ("ASoC: intel: cht_bsw_max98090_ti: Add quirk for
boards using pmc_plt_clk_0") and making use of the existing
dmi_check_system() call and related infrastructure added in
commit 22af29114eb4 ("ASoC: Intel: cht-bsw-rt5645: add quirks for
SSP0/AIF1/AIF2 routing").
Signed-off-by: Sam McNally <sammc@chromium.org>
Acked-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20190917054933.209335-1-sammc@chromium.org
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions