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authorJiri Pirko <jiri@mellanox.com>2019-03-24 11:14:34 +0100
committerDavid S. Miller <davem@davemloft.net>2019-03-24 14:55:31 -0400
commitfaaccbe6eb07ecd590bebae11eb236661ecfb069 (patch)
tree1418b6abf2203ef36e8619413da70a93d988e953 /tools/perf/scripts/python/exported-sql-viewer.py
parentnet: devlink: disallow port_attrs_set() to be called before register (diff)
nfp: move devlink port type set after netdev registration
Similar to other driver, move the port type set after netdev registration is done. Along with that, clear the type before unregistration. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions
Copyright © 1996 – 2026 Jason A. Donenfeld. All Rights Reverse Engineered.
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/* Copyright (C) 2002-2018 Free Software Foundation, Inc.
   This file is part of the GNU C Library.
   Contributed by Ulrich Drepper <drepper@redhat.com>, 2002.

   The GNU C Library is free software; you can redistribute it and/or
   modify it under the terms of the GNU Lesser General Public
   License as published by the Free Software Foundation; either
   version 2.1 of the License, or (at your option) any later version.

   The GNU C Library is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
   Lesser General Public License for more details.

   You should have received a copy of the GNU Lesser General Public
   License along with the GNU C Library; if not, see
   <http://www.gnu.org/licenses/>.  */

/* Default stack size.  */
#define ARCH_STACK_DEFAULT_SIZE	(2 * 1024 * 1024)

/* Required stack pointer alignment at beginning.  SSE requires 16
   bytes.  */
#define STACK_ALIGN		16

/* Minimal stack size after allocating thread descriptor and guard size.  */
#define MINIMAL_REST_STACK	2048

/* Alignment requirement for TCB.

   Some processors such as Intel Atom pay a big penalty on every
   access using a segment override if that segment's base is not
   aligned to the size of a cache line.  (See Intel 64 and IA-32
   Architectures Optimization Reference Manual, section 13.3.3.3,
   "Segment Base".)  On such machines, a cache line is 64 bytes.  */
#define TCB_ALIGNMENT		64


/* Location of current stack frame.  */
#define CURRENT_STACK_FRAME	__builtin_frame_address (0)