diff options
| author |   Tim Huang <tim.huang@amd.com> | 2022-08-15 13:03:49 +0800 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2022-08-22 16:47:09 -0400 |
| commit | 6575eb930d16b789a0230df5664578d7d159a255 (patch) | |
| tree | 7d74111fbffaf1bb28f68b553378f2d5dcbc3623 /tools/perf/scripts/python/flamegraph.py | |
| parent | drm/radeon: add a force flush to delay work when radeon (diff) | |
drm/amdgpu: add TX_POWER_CTRL_1 macro definitions for NBIO IP v7.7.0
Add the BIF0_PCIE_TX_POWER_CTRL_1 register offset and mask macro
definitions for AMD_CG_SUPPORT_BIF_LS.
Signed-off-by: Tim Huang <tim.huang@amd.com>
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/flamegraph.py')
0 files changed, 0 insertions, 0 deletions