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| author |   Saeed Mahameed <saeedm@mellanox.com> | 2019-07-29 21:12:56 +0000 |
|---|---|---|
| committer | Saeed Mahameed <saeedm@mellanox.com> | 2019-08-01 11:14:24 -0700 |
| commit | 7761f9eef3f09f2f4c579313e0c536770b5ecff4 (patch) | |
| tree | b5b4586787179a195fd0c7c5cc0ffbe40443f07b /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | net/mlx5: Add flow counter bulk allocation hardware bits and command (diff) | |
| download | linux-dev-7761f9eef3f09f2f4c579313e0c536770b5ecff4.tar.xz linux-dev-7761f9eef3f09f2f4c579313e0c536770b5ecff4.zip | |
net/mlx5: Fix offset of tisc bits reserved field
First reserved field is off by one instead of reserved_at_1 it should be
reserved_at_2, fix that.
Fixes: a12ff35e0fb7 ("net/mlx5: Introduce TLS TX offload hardware bits and structures")
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
Reviewed-by: Leon Romanovsky <leonro@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions