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authorJ. German Rivera <German.Rivera@freescale.com>2016-01-06 16:03:23 -0600
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2016-02-07 19:10:12 -0800
commit89f067df928b9bfc53430b09aa4ac894f34f7340 (patch)
tree5cbcb34a81d14e101814e2c59e1a72ee8a8c4bf6 /tools/perf/scripts/python/netdev-times.py
parentstaging: fsl-mc: Added GICv3-ITS support for FSL-MC MSIs (diff)
staging: fsl-mc: Extended MC bus allocator to include IRQs
All the IRQs for DPAA2 objects in the same DPRC must use the ICID of that DPRC, as their device Id in the GIC-ITS. Thus, all these IRQs must share the same ITT table in the GIC. As a result, a pool of IRQs with the same device Id must be preallocated per DPRC (fsl-mc bus instance). So, the fsl-mc bus object allocator is extended to also provide services to allocate IRQs to DPAA2 devices, from their parent fsl-mc bus IRQ pool. Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'tools/perf/scripts/python/netdev-times.py')
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