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| author | 2017-06-09 15:26:03 -0700 | |
|---|---|---|
| committer | 2017-06-12 09:42:06 -0700 | |
| commit | 8b0f7e06895c0d5f3cc28e494c7816e728d40f35 (patch) | |
| tree | 25a7c5689fd32c857c16805103ea1eeb45afea0e /tools/perf/scripts/python/sctop.py | |
| parent | drm/i915/cnl: DDI - PLL mapping (diff) | |
| download | linux-dev-8b0f7e06895c0d5f3cc28e494c7816e728d40f35.tar.xz linux-dev-8b0f7e06895c0d5f3cc28e494c7816e728d40f35.zip | |
drm/i915: Configure DPLL's for Cannonlake
DPLL's are defined in DPCLKA_CFGCR0 register (0x6C200). Let's use these
definitions when computing dpll's for ddi ports.
v2: (Rodrigo) Remove register that was defined in another patch with
fixed name and more bits.
Signed-off-by: Kahola, Mika <mika.kahola@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1497047175-27250-6-git-send-email-rodrigo.vivi@intel.com
Diffstat (limited to 'tools/perf/scripts/python/sctop.py')
0 files changed, 0 insertions, 0 deletions
