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| author |   Robert Hancock <robert.hancock@calian.com> | 2022-03-04 20:24:40 -0600 |
|---|---|---|
| committer |   David S. Miller <davem@davemloft.net> | 2022-03-05 11:12:08 +0000 |
| commit | 0155ae6eb84dbeecb7199a2fd9dee72e046ac875 (patch) | |
| tree | 2e8813bf924c2f42dc5d9283e928956e44bf94c0 /tools/perf/scripts/python/stackcollapse.py | |
| parent | net: axienet: Clean up DMA start/stop and error handling (diff) | |
| download | linux-dev-0155ae6eb84dbeecb7199a2fd9dee72e046ac875.tar.xz linux-dev-0155ae6eb84dbeecb7199a2fd9dee72e046ac875.zip | |
net: axienet: don't set IRQ timer when IRQ delay not used
When the RX or TX coalesce count is set to 1, there's no point in
setting the delay timer value since an interrupt will already be raised
on every packet, and the delay interrupt just causes extra pointless
interrupts.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions