diff options
| author |   Alexander Kochetkov <al.kochet@gmail.com> | 2016-03-06 13:04:17 +0300 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2016-03-06 18:36:13 +0700 |
| commit | 0277e01aebc8895198a4717ccaf7e4fcf39ada78 (patch) | |
| tree | ae922954695c781e170436c8cb313c54c6aefb90 /tools/perf/scripts/python/stackcollapse.py | |
| parent | spi/rockchip: Make sure spi clk is on in rockchip_spi_set_cs (diff) | |
| download | linux-dev-0277e01aebc8895198a4717ccaf7e4fcf39ada78.tar.xz linux-dev-0277e01aebc8895198a4717ccaf7e4fcf39ada78.zip | |
spi/rockchip: fix endian mode for 16-bit transfers
16-bit transfers must be in big endian mode on wire.
Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions