diff options
| author |   Naveen Mamindlapalli <naveenm@marvell.com> | 2022-09-10 13:24:16 +0530 |
|---|---|---|
| committer |   David S. Miller <davem@davemloft.net> | 2022-09-17 20:13:41 +0100 |
| commit | 85a5f9638313a1df7e84e9ea66ecd216133215c2 (patch) | |
| tree | 20f8b43d78dc13bdc85ac9b8e43a2838f741fdd5 /tools/perf/scripts/python/stackcollapse.py | |
| parent | octeontx2-af: Add PTP PPS Errata workaround on CN10K silicon (diff) | |
octeontx2-af: Initialize PTP_SEC_ROLLOVER register properly
Since the reset value of PTP_SEC_ROLLOVER is incorrect on
CNF10KB silicon, the ptp timestamps are inaccurate. This
patch initializes the PTP_SEC_ROLLOVER register properly
for the CNF10KB silicon.
Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com>
Signed-off-by: Sunil Kovvuri Goutham <sgoutham@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions