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| author |   Mahesh Kumar <mahesh1.kumar@intel.com> | 2018-04-09 09:11:06 +0530 |
|---|---|---|
| committer |   Maarten Lankhorst <maarten.lankhorst@linux.intel.com> | 2018-04-09 13:37:38 +0200 |
| commit | 8b2b53ce94e808ef9340add94c4c50b9e5267413 (patch) | |
| tree | 7c2d3fadcb0838a7bab0cc3ef3c206e1749d58e4 /tools/perf/scripts/python/stackcollapse.py | |
| parent | drm/i915/skl+: pass skl_wm_level struct to wm compute func (diff) | |
| download | linux-dev-8b2b53ce94e808ef9340add94c4c50b9e5267413.tar.xz linux-dev-8b2b53ce94e808ef9340add94c4c50b9e5267413.zip | |
drm/i915/skl+: make sure higher latency level has higher wm value
DDB allocation optimization algorithm requires/assumes ddb allocation for
any memory C-state level DDB value to be as high as level below the
current level. Render decompression requires level WM to be as high as
wm level-0. This patch fulfils both the requirements.
v2: Changed plane_num to plane_id in skl_compute_wm_levels
v3: Addressed review comments from Shashank Sharma
Changed the commit message "statement can be more clear,
"DDB value to be as high as level below " what is level below ?"
v4: Added reviewed by tag from Shashank Sharma
v5: Added reviewed by from Juha-Pekka Heikkila
v6: Rebased the series
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1523245273-30264-8-git-send-email-vidya.srinivas@intel.com
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
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