diff options
| author |   Matt Roper <matthew.d.roper@intel.com> | 2020-05-04 15:52:13 -0700 |
|---|---|---|
| committer |   Lucas De Marchi <lucas.demarchi@intel.com> | 2020-05-20 08:35:22 -0700 |
| commit | 93e2323b5c85a2b7ac4260d720de26ca5d5ad796 (patch) | |
| tree | c8516f959d702cb9a08b91deb487a95983d4309e /tools/perf/scripts/python/stackcollapse.py | |
| parent | drm/i915/rkl: Limit number of universal planes to 5 (diff) | |
drm/i915/rkl: Add power well support
RKL power wells are similar to TGL power wells, but have some important
differences:
* PG1 now has pipe A's VDSC (rather than sticking it in PG2)
* PG2 no longer exists
* DDI-C (aka TC-1) moves from PG1 -> PG3
* PG5 no longer exists due to the lack of a fourth pipe
Also note that what we refer to as 'DDI-C' and 'DDI-D' need to actually
be programmed as TC-1 and TC-2 even though this platform doesn't have TC
outputs.
Bspec: 49234
Cc: Imre Deak <imre.deak@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200504225227.464666-9-matthew.d.roper@intel.com
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
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